IBM 7030 Stretch

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IBM Stretch

IBM 7030 maintenance console at the

, Paris

Design

Manufacturer

Designer

Release date

May 1961

Units sold

Price

US$7,780,000 (equivalent to

$83,820,000 in 2025)

Casing

Weight

70,000 pounds (35 short

tons; 32 t)

Power

100

@ 110 V

System

MCP

processor

128 to 2048

(16,384 x 64 to 262,144 x

64 bits)

1.2 MIPS

Operator console at the

The

IBM 7030

, also known as

Stretch

, was

's first

. It was the fastest computer in the world from 1961 until the

first

became operational in 1964.

Originally designed to meet a requirement formulated by

, the first example was delivered to

in 1961, and a second customized version, the

, to the

in 1962. The Stretch at the

, England was heavily

used by researchers there and at

, but only after the development

of the S2

compiler which was the first to add

, and

which was later ported to the

Chilton.

The 7030 was much slower than expected and failed to meet its aggressive

performance goals. IBM was forced to drop its price from $13.5 million to

only $7.78 million and withdrew the 7030 from sales to customers beyond those

having already negotiated contracts.

magazine named Stretch one of

the biggest project management failures in

history.

Within IBM, being eclipsed by the smaller

seemed

hard to accept.

The project lead,

was initially made

a scapegoat for his role in the "failure" but,

after the success of the

became obvious, he received an official apology, and in 1966 was

made an

In spite of the failure of Stretch to meet IBM's performance goals, it served

as the basis for many of the design features of the successful IBM System/360,

which was announced in 1964 and first shipped in 1965.

Development history

[

]

In early 1955, Dr.

of the

wanted a new scientific computing system for three-dimensional

calculations. Proposals were requested from IBM and

for

this new system, to be called

Livermore Automatic Reaction Calculator

. According to IBM executive

, such a system would cost

roughly $2.5 million and would run at one to two

: 12

Delivery was to

be two to three years after the contract was signed.

At IBM, a small team at

including John Griffith and

worked on the design proposal. Just after they finished and were about to

present the proposal, Ralph Palmer stopped them and said, "It's a mistake."

: 12

The proposed design would have been built with either

, both likely to be soon outperformed by the then newly

invented

: 12

IBM returned to Livermore and stated that they were withdrawing from the contract, and instead proposed a dramatically

better system, "We are not going to build that machine for you; we want to build something better! We do not know

precisely what it will take but we think it will be another million dollars and another year, and we do not know how

fast it will run but we would like to shoot for ten million instructions per second."

: 13

Livermore was not

impressed, and in May 1955 they announced that UNIVAC had won the

contract, now called the

Livermore Automatic

Research Computer

. LARC would eventually be delivered in June 1960.

In September 1955, fearing that

might also order a LARC, IBM submitted a preliminary

proposal for a high-performance binary computer based on the improved version of the design that Livermore had

rejected, which they received with interest. In January 1956, Project Stretch was formally initiated. In November

1956, IBM won the contract with the aggressive performance goal of a "speed at least 100 times the

" (i.e. 4

MIPS). Delivery was slated for 1960.

During design, it proved necessary to reduce the clock speeds, making it clear that Stretch could not meet its

aggressive performance goals, but estimates of performance ranged from 60 to 100 times the IBM 704. In 1960, the price

of $13.5 million was set for the IBM 7030. In 1961, actual

indicated that the performance of the IBM 7030

was only about 30 times the IBM 704 (i.e. 1.2 MIPS), causing considerable embarrassment for IBM. In May 1961,

announced a price cut of all 7030s under negotiation to $7.78 million and immediate withdrawal of the

product from further sales.

Its

addition time is 1.38–1.50

, multiplication time is 2.48–2.70 microseconds, and

division time is 9.00–9.90 microseconds.

Technical impact

[

]

While the IBM 7030 was not considered successful, it spawned many technologies incorporated in future machines that

were highly successful. The

(SMS)

logic was the basis for the

line of

scientific computers, the

and

business computers, the

and

lines, and the

small scientific computer; the 7030 used about 170,000 transistors. The

Model I Core Storage units were also

used in the IBM 7090, IBM 7070 and IBM 7080.

, memory protection, generalized interrupts, the

for I/O

were all concepts later incorporated in the

line of computers as well as most later

(CPU).

Stephen Dunwell, the project manager who became a scapegoat when Stretch failed commercially, pointed out soon after

the phenomenally successful 1964 launch of System/360 that most of its core concepts were pioneered by Stretch.

1966, he had received an apology and been made an IBM Fellow, a high honor that carried with it resources and

authority to pursue one's desired research.

and decoding, and

were used in later supercomputer designs such

as the IBM System/360 Models

and

, and the

series as well as computers from other manufacturers. As

of 2021

, these techniques are still used in most advanced microprocessors, starting with the 1990s generation that

included the Intel

and the Motorola/IBM

, as well as in many embedded microprocessors and

microcontrollers from various manufacturers.

Hardware implementation

[

]

A circuit board from the IBM

7030, in the

The 7030 CPU uses

(originally called

current-steering

logic

)

on 18 types of

cards. It uses 4,025 double cards

(as shown) and 18,747 single cards, holding 169,100 transistors, requiring a total

of 21 kW power.

: 54

It uses high-speed NPN and PNP germanium

with cut-off frequency over 100 MHz, and using ~50 mW each.

: 57

Some

third level

circuits use a third voltage level. Each logic level has a delay of about 20 ns. To gain speed in critical areas

is used to reduce the delay to about 10 ns.

: 55

It uses the same core memory as the

: 58

Installations

[

]

(LASL) in April 1961, accepted in May 1961, and used until June 21, 1971.

delivered November 1961.

U.S.

in February 1962 as the main CPU of the

system, used until 1976,

when the

Tractor tape system developed problems due to worn cams that could not be replaced.

, England, delivered February 1962

Washington D.C., delivered June/July 1962.

, delivered December 1962.

and used until August 1971. In the spring of 1972, it was sold to

, where it was used by the physics department until scrapped in 1982.

U.S. Navy

, delivered Sep/Oct 1962.

, France, delivered November 1963.

IBM.

The Lawrence Livermore Laboratory's IBM 7030 (except for its

) and portions of the MITRE

Corporation/Brigham Young University IBM 7030 now reside in the

collection, in

Architecture

[

]

Data formats

[

]

are variable in length, stored in either binary (1 to 64 bits) or decimal (1 to 16 digits) and

either unsigned format or

. Fields may straddle word boundaries. In decimal format, digits are

variable length bytes (four to eight bits).

numbers have a 1-bit exponent flag, a 10-bit exponent, a 1-bit exponent sign, a 48-bit magnitude,

and a 4-bit sign byte in sign/magnitude format.

Alphanumeric characters are variable length and can use any character code of 8 bits or less.

Bytes are variable length (one to eight bits).

Instruction format

[

]

Instructions are either 32-bit or 64-bit.

Registers

[

]

The registers overlay the first 32 addresses of memory as shown.

Address

Mnemonic

Stored

in:

64-bit zero: always reads as zero, cannot be changed by writes

Main core

storage

$IT

Interval timer (bits 0–18): decremented at 1024 Hz, recycles about every 8.5 minutes;

at zero turns the

time signal indicator

on in the indicator register

Index core

storage

$TC

36-bit time clock (bits 28–63): count of 1024 Hz ticks. Bits 38–63 are incremented

(i.e. bit 38 changes) once per second. Recycles every ~777 days.

$IA

18-bit interruption address

Main core

storage

$UB

18-bit upper-boundary address (bits 0–17)

Transistor

$LB

18-bit lower-boundary address (bits 32–49)

1-bit boundary control (bit 57): determines whether addresses within or outside the

boundary addresses are protected

64-bit maintenance bits: only used for maintenance

Main core

storage

$CA

Channel address (bits 12–18): read-only, set by the

exchange

, an I/O processor

Transistor

$CPUS

Other CPU bits (bits 0–18): signaling mechanism for a cluster of up to 20 CPUs

Transistor

$LZC

Left zeroes count (bits 17–23): number of leading zero bits from a connective result

or floating point operation

Transistor

$AOC

All-ones count (bits 44–50): count of bits set in connective result or decimal

multiplication or division

Left half of 128-bit

Transistor

Right half of 128-bit accumulator

$SB

Accumulator sign byte (bits 0–7)

$IND

Indicator register (bits 0–19)

Transistor

$MASK

64-bit mask register: bits 0–19 always 1, bits 20–47 writable, bits 48–63 always 0

Transistor

$RM

64-bit remainder register: set by integer and floating-point

divide

instructions only

Main core

storage

$FT

64-bit factor register: changed only by the

load factor

instruction

Main core

storage

$TR

64-bit transit register

Main core

storage

...

$X0

...

$X15

64-bit index registers (sixteen)

Index core

storage

The accumulator and index registers operate in

format.

Memory

[

]

Main memory is 16K to 256K 64-bit binary words, in banks of 16K.

The memory was immersion oil-heated/cooled to stabilize its operating characteristics.

Software

[

]

(STRAP)

MCP (not to be confused with the

)

COLASL

and IVY programming languages

programming language

SOS (Stretch Operating System), written at the BYU Scientific Computing Center as an upgrade to MCP, along with an

updated variant of FORTRAN